HD64F36022 datasheet(247/384 Pages) RENESAS

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Section 14 A/D Converter

Rev. 4.00 Sep. 23, 2005 Page 221 of 354

REJ09B0025-0400

14.3.2

A/D Control/Status Register (ADCSR)

ADCSR consists of the control bits and conversion end status bits of the A/D converter.

Bit

Bit Name

Initial

Value

R/W

Description

ADF

R/W

A/D End Flag

[Setting conditions]

• When A/D conversion ends in single mode

• When A/D conversion ends on all the channels

selected in scan mode

[Clearing conditions]

• When 0 is written after reading ADF = 1

ADIE

R/W

A/D Interrupt Enable

A/D conversion end interrupt (ADI) request enabled by

ADF when 1 is set

ADST

R/W

A/D Start

Setting this bit to 1 starts A/D conversion. In single mode,

this bit is cleared to 0 automatically when conversion on

the specified channel is complete. In scan mode,

conversion continues sequentially on the specified

channels until this bit is cleared to 0 by software, a reset,

or a transition to standby mode.

SCAN

R/W

Scan Mode

Selects single mode or scan mode as the A/D conversion

operating mode.

0: Single mode

1: Scan mode

CKS

R/W

Clock Select

Selects the A/D conversions time

0: Conversion time = 134 states (max.)

1: Conversion time = 70 states (max.)

Clear the ADST bit to 0 before switching the conversion

time.

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