Electronic Components Datasheet Search
  English  ▼

X  

HD64F36022 Datasheet(PDF) 250 Page - Renesas Technology Corp

Part # HD64F36022
Description  Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
PDF  384 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F36022 Datasheet(HTML) 250 Page - Renesas Technology Corp

Back Button HD64F36022 Datasheet HTML 246Page - Renesas Technology Corp HD64F36022 Datasheet HTML 247Page - Renesas Technology Corp HD64F36022 Datasheet HTML 248Page - Renesas Technology Corp HD64F36022 Datasheet HTML 249Page - Renesas Technology Corp HD64F36022 Datasheet HTML 250Page - Renesas Technology Corp HD64F36022 Datasheet HTML 251Page - Renesas Technology Corp HD64F36022 Datasheet HTML 252Page - Renesas Technology Corp HD64F36022 Datasheet HTML 253Page - Renesas Technology Corp HD64F36022 Datasheet HTML 254Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 250 / 384 page
background image
Section 14 A/D Converter
Rev. 4.00 Sep. 23, 2005 Page 224 of 354
REJ09B0025-0400
14.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
D) has passed after the ADST bit is set to 1, then
starts conversion. Figure 14.2 shows the A/D conversion timing. Table 14.3 shows the A/D
conversion time.
As indicated in figure 14.2, the A/D conversion time includes t
D and the input sampling time. The
length of t
D varies depending on the timing of the write access to ADCSR.
The total conversion
time therefore varies within the ranges indicated in table 14.3.
In scan mode, the values given in table 14.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states
(fixed) when CKS = 1.
(1)
(2)
tD
tSPL
tCONV
ø
Address
Write signal
Input sampling
timing
ADF
Legend
(1)
: ADCSR write cycle
(2)
: ADCSR address
tD
: A/D conversion start delay
tSPL
: Input sampling time
tCONV : A/D conversion time
Figure 14.2 A/D Conversion Timing



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com