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HD64F36022 Datasheet(PDF) 250 Page - Renesas Technology Corp |
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HD64F36022 Datasheet(HTML) 250 Page - Renesas Technology Corp |
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250 / 384 page ![]() Section 14 A/D Converter Rev. 4.00 Sep. 23, 2005 Page 224 of 354 REJ09B0025-0400 14.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (t D) has passed after the ADST bit is set to 1, then starts conversion. Figure 14.2 shows the A/D conversion timing. Table 14.3 shows the A/D conversion time. As indicated in figure 14.2, the A/D conversion time includes t D and the input sampling time. The length of t D varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 14.3. In scan mode, the values given in table 14.3 apply to the first conversion time. In the second and subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states (fixed) when CKS = 1. (1) (2) tD tSPL tCONV ø Address Write signal Input sampling timing ADF Legend (1) : ADCSR write cycle (2) : ADCSR address tD : A/D conversion start delay tSPL : Input sampling time tCONV : A/D conversion time Figure 14.2 A/D Conversion Timing |
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