HD64F36022 datasheet(246/384 Pages) RENESAS

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Section 14 A/D Converter

Rev. 4.00 Sep. 23, 2005 Page 220 of 354

REJ09B0025-0400

14.3

The A/D converter has the following registers.

• A/D data register A (ADDRA)

• A/D data register B (ADDRB)

• A/D data register C (ADDRC)

• A/D data register D (ADDRD)

• A/D control/status register (ADCSR)

• A/D control register (ADCR)

14.3.1

A/D Data Registers A to D (ADDRA to ADDRD)

There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of

A/D conversion. The ADDR registers, which store a conversion result for each channel, are

shown in table 14.2.

The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.

The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read

directly from the CPU, however the lower byte should be read via a temporary register. The

temporary register contents are transferred from the ADDR when the upper byte data is read.

Therefore byte access to ADDR should be done by reading the upper byte first then the lower one.

Word access is also possible. ADDR is initialized to H'0000.

Table 14.2

Analog Input Channels and Corresponding ADDR Registers

Analog Input Channel

A/D Data Register to Be Stored Results of A/D Conversion

AN0

ADDRA

AN1

ADDRB

AN2

ADDRC

AN3

ADDRD

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