SH7101 datasheet(362/560 Pages) RENESAS

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Section 10 Serial Communication Interface (SCI)

Rev.1.00 Sep. 18, 2008 Page 328 of 522

REJ09B0069-0100

10.8.5

Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)

Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if

the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting

transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared

to 0.

10.8.6

Cautions on Clocked Synchronous External Clock Mode

1. Set TE = RE = 1 only when external clock SCK is 1.

2. Do not set TE = RE = 1 until at least four P

φ clocks after external clock SCK has changed

from 0 to 1.

3. When receiving, RDRF is 1 when RE is cleared to 0 after 2.5 to 3.5 P

φ clocks from the rising

edge of the SCK input of the D7 bit in RxD, but copying to RDR is not possible.

10.8.7

Caution on Clocked Synchronous Internal Clock Mode

When receiving, RDRF is 1 when RE is cleared to 0 after 1.5 P

φ clocks from the rising edge of the

SCK output of the D7 bit in RxD, but copying to RDR is not possible.

SH7101 Datasheet(PDF) 362 Page - Renesas Technology Corp