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SH7101 Datasheet(PDF) 360 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  560 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 360 Page - Renesas Technology Corp

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Section 10 Serial Communication Interface (SCI)
Rev.1.00 Sep. 18, 2008 Page 326 of 522
REJ09B0069-0100
10.7
Interrupt Sources
10.7.1
Interrupts in Normal Serial Communication Interface Mode
Table 10.10 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND
flag in SSR is set to 1, a TEI interrupt request is generated.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated.
A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Table 10.10 SCI Interrupt Sources
Channel
Name
Interrupt Source
Interrupt Flag
ERI_2
Receive error
ORER, FER, PER
RXI_2
Receive data full
RDRF
TXI_2
Transmit data empty
TDRE
2
TEI_2
Transmission end
TEND
3
ERI_3
Receive error
ORER, FER, PER
RXI_3
Receive data full
RDRF
TXI_3
Transmit data empty
TDRE
TEI_3
Transmission end
TEND



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