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SH7101 Datasheet(PDF) 356 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  560 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 356 Page - Renesas Technology Corp

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Section 10 Serial Communication Interface (SCI)
Rev.1.00 Sep. 18, 2008 Page 322 of 522
REJ09B0069-0100
10.6.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 10.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
or output, starts receiving data, and stores the received data in RSR.
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt processing routine reads the receive data transferred to
RDR before reception of the next receive data has finished, continuous reception can be
enabled.
Bit 7
Serial data
Synchroniza-
tion clock
1 frame
RDRF
ORER
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RXI interrupt
request
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
processing routine
ERI interrupt
request generated
by overrun error
RXI interrupt
request
generated
Figure 10.18 Example of SCI Operation in Reception



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