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SH7101 Datasheet(PDF) 481 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 481 Page - Renesas Technology Corp |
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481 / 560 page ![]() Section 17 RAM Rev.1.00 Sep. 18, 2008 Page 447 of 522 REJ09B0069-0100 Section 17 RAM This LSI has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU via a 32-bit data bus, enabling 8, 16, or 32-bit width access to data in the on-chip RAM. Data in the on- chip RAM can always be accessed in one cycle, providing high-speed access that makes this RAM ideal for use as a program area, stack area, or data area. The contents of the on-chip RAM are retained in both sleep and software standby modes. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 18.2.2, System Control Register (SYSCR). Product Type Type of ROM RAM Capacity RAM Address SH7108 Masked ROM 4 kbytes H'FFFFF000 to H'FFFFFFFF 17.1 Usage Note • Module Standby Mode Setting RAM can be enabled or disabled by the module standby control register. The initial value enables RAM operation. RAM access is disabled by setting module standby mode. For details, refer to section 18, Power-Down Modes. |
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