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SH7101 Datasheet(PDF) 484 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 484 Page - Renesas Technology Corp |
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484 / 560 page ![]() Section 18 Power-Down Modes Rev.1.00 Sep. 18, 2008 Page 450 of 522 REJ09B0069-0100 Table 18.1 Internal Operating States in Each Mode Function Normal operation Sleep Module Standby Software Standby Hardware Standby System clock pulse generator Functioning Functioning Functioning Halted Halted Instructions CPU Registers Functioning Halted (retained) Functioning Halted (retained) Halted (undefined) NMI Functioning Functioning Functioning Functioning Halted External interrupts IRQ3 to IRQ0 Peripheral functions I/O ports Functioning Functioning Functioning Retained High impedance WDT Functioning Functioning Functioning Halted (retained) Halted (reset) SCI A/D MTU CMT MMT Functioning Functioning Halted (reset) Halted (reset) Halted (reset) ROM Functioning Functioning Halted (reset) Halted (reset) Halted (reset) RAM Functioning Functioning Retained Retained Retained Notes: "Halted (retained)" means that the operation of the internal state is suspended, although internal register values are retained. "Halted (reset)" means that internal register values and internal state are initialized. In module standby mode, only modules for which a stop setting has been made are halted (reset or retained). 1. There are two types of on-chip peripheral module registers; ones which are initialized in software standby mode and module standby mode, and those not initialized in those modes. For details, refer to section 19.3, Register States in Each Operating Mode. 2. The port high-impedance bit (Hi-Z) in SBYCR sets the state of the I/O ports in software standby mode. For details on the setting, refer to section 18.2.1, Standby Control Register (SBYCR). For the state of pins, refer to appendix A, Pin States. |
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