SH7101 datasheet(487/560 Pages) RENESAS

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Section 18 Power-Down Modes

Rev.1.00 Sep. 18, 2008 Page 453 of 522

REJ09B0069-0100

18.2.1

Standby Control Register (SBYCR)

SBYCR is an 8-bit readable/writable register that performs software standby mode control.

Bit

Bit Name

Initial

Value

R/W

Description

SSBY

R/W

Software Standby

Specifies the transition mode after executing the SLEEP

instruction.

0: Transition to sleep mode after the SLEEP instruction

has been executed

1: Transition to software standby mode after the SLEEP

instruction has been executed

This bit cannot be set to 1 when the watchdog timer

(WDT) is operating (when the TME bit in TCSR of the

WDT is set to 1). When entering software standby mode,

clear the TME bit to 0, stop the WDT, then set the SSBY

bit to 1.

HIZ

R/W

Port High-Impedance

In software standby mode, this bit selects whether the pin

state of the I/O port is retained or changed to high-

impedance.

0: In software standby mode, the pin state is retained.

1: In software standby mode, the pin state is changed to

high-impedance.

The HIZ bit cannot be set to 1 when the TEM bit in TCSR

of the WDT is set to 1.

When changing the pin state of the I/O port to high-

impedance, clear the TEM bit to 0, then set the HIZ bit to

⎯

Reserved

This bit is always read as 0. The write value should always

be 0.

4 to 1

⎯

All 1

Reserved

These bits are always read as 1. The write value should

always be 1.

IRQEL

R/W

IRQ3 to IRQ0 Enable

Enables to clear software standby mode by IRQ interrupts.

0: Software standby mode is cleared.

1: Software standby mode is not cleared.

SH7101 Datasheet(PDF) 487 Page - Renesas Technology Corp

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