SH7101 datasheet(490/560 Pages) RENESAS

490 / 560 page

Section 18 Power-Down Modes

Rev.1.00 Sep. 18, 2008 Page 456 of 522

REJ09B0069-0100

• MSTCR2

Bit

Bit Name

Initial

Value

R/W

Description

⎯

Reserved

This bit is always read as 1. The write value should

always be 1.

MSTP14

R/W

Motor management timer (MMT)

MSTP13

R/W

Multifunction timer pulse unit (MTU)

MSTP12

R/W

Compare match timer (CMT)

11 to 8

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0

⎯

Reserved

This bit is always read as 1. The write value should

always be 1.

MSTP6

R/W

A/D converter (A/D2)

MSTP5

R/W

A/D converter (A/D1)

MSTP4

R/W

A/D converter (A/D0)

3 to 0

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

18.3

Operation

18.3.1

Sleep Mode

(1) Transition to Sleep Mode

If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the CPU enters

sleep mode. In sleep mode, CPU operation stops, however the contents of the CPU's internal

registers are retained. Peripheral functions except the CPU do not stop.

(2) Clearing Sleep Mode

Sleep mode is cleared by the conditions below.

• Clearing by a power-on reset

When the

RES pin is driven low, the CPU enters the reset state. When the RES pin is driven

high after the elapse of the specified reset input period, the CPU starts the reset exception

handling.

SH7101 Datasheet(PDF) 490 Page - Renesas Technology Corp

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