SH7101 datasheet(491/560 Pages) RENESAS

491 / 560 page

Section 18 Power-Down Modes

Rev.1.00 Sep. 18, 2008 Page 457 of 522

REJ09B0069-0100

When an internal power-on reset by the WDT occurs, sleep mode is also cleared.

• Clearing by a manual reset

When the

MRES pin is driven low while the RES pin goes high, the CPU shifts to the manual

reset state and thus sleep mode is cleared.

When an internal manual reset by the WDT occurs, sleep mode is also cleared.

18.3.2

Software Standby Mode

(1) Transition to Software Standby Mode

A transition is made to software standby mode if the SLEEP instruction is executed while the

SSBY bit in SBYCR is set to 1. In this mode, the CPU, on-chip peripheral functions, and

oscillator, all stop.

However, the contents of the CPU's internal registers and on-chip RAM data (when the RAME bit

in SYSCR is 0) are retained as long as the specified voltage is supplied. There are two types of on-

chip peripheral module registers; ones which are initialized by software standby mode, and those

not initialized by that mode. For details, refer to section 19.3, Register States in Each Operating

Mode. The port high-impedance bit (HIZ) in SBYCR sets the state of the I/O port either to

"retained" or "high-impedance". For the state of pins, refer to appendix A, Pin States. In software

standby mode, the oscillator stops and thus power consumption is significantly reduced.

SH7101 Datasheet(PDF) 491 Page - Renesas Technology Corp