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SH7101 Datasheet(PDF) 496 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 496 Page - Renesas Technology Corp |
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496 / 560 page  Section 18 Power-Down Modes Rev.1.00 Sep. 18, 2008 Page 462 of 522 REJ09B0069-0100 When an on-chip peripheral module is in module standby mode, read/write access to its registers is disabled. 18.4 Usage Notes 18.4.1 I/O Port Status When a transition is made to software standby mode while the port high-impedance bit (HIZ) in SBYCR is cleared to 0, I/O port states are retained. Therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 18.4.2 Current Consumption during Oscillation Stabilization Wait Period Current consumption increases during the oscillation stabilization wait period. 18.4.3 On-Chip Peripheral Module Interrupt Relevant interrupt operations cannot be performed in module standby mode. Consequently, if the CPU enters module standby mode while an interrupt has been requested, it will not be possible to clear the CPU interrupt source. Interrupts should therefore be disabled before entering module standby mode. 18.4.4 Writing to MSTCR1 and MSTCR2 MSTCR1 and MSTCR2 should only be written to by the CPU. |
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