SH7101 datasheet(129/560 Pages) RENESAS

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Section 7 Bus State Controller (BSC)

Rev.1.00 Sep. 18, 2008 Page 95 of 522

REJ09B0069-0100

7.2

Input/Output Pins

Table 7.1 lists bus state controller pins of the SH7109. The SH7108 is not equipped with this type

of pins.

Table 7.1

Pin Configuration

Name

Abbr.

I/O

Description

Address bus

A17 to A0

Output

Address output

Data bus

D7 to D0

I/O

8-bit data bus

Chip select

CS0

Output

Chip select signal indicating the area being

accessed

Read

Output

Strobe signal that indicates the read cycle

Lower byte write

WRL

Output

Strobe signal that indicates a write cycle to the lower

8 bits (D7 to D0)

Wait

WAIT

Input

Wait state request signal

Bus request

BREQ

Input

Bus release request input

Bus request

acknowledge

BACK

Output

Bus use enable output

7.3

The following registers are provided for the bus state controller. For details on addresses and states

of these registers in each processing, refer to section 19, List of Registers.

These registers are used to control wait states, bus width, and interfaces with memories like ROM

and SRAM. All registers are 16 bits.

• Bus control register 1 (BCR1)

• Bus control register 2 (BCR2)

• Wait control register 1 (WCR1)

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