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SH7101 Datasheet(PDF) 130 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 130 Page - Renesas Technology Corp |
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130 / 560 page  Section 7 Bus State Controller (BSC) Rev.1.00 Sep. 18, 2008 Page 96 of 522 REJ09B0069-0100 7.4 Address Map Figure 7.2 shows the address format used by this LSI. Output address: Output from the address pins CS space selection: Decoded, outputs when A31 to A24 = 00000000 Space selection: Not output externally; used to select the type of space On-chip ROM space or CS0 space when 00000000 (H'00) Reserved (do not access) when 00000001 to 11111110 (H'01 to H'FE) On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF) A31 to A24 A23, A22 A21 to A18 A0 A17 Figure 7.2 Address Format This chip uses 32-bit addresses: • Bits A31 to A24 are used to select the type of space and are not output externally. • Bits A23 and A22 are decoded and output as chip select signals (CS0) for the corresponding areas when bits A31 to A24 are 00000000. • A17 to A0 are output externally. A21 to A18 are not output externally. Table 7.2 shows the address map. |
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