SH7101 datasheet(147/560 Pages) RENESAS

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Section 7 Bus State Controller (BSC)

Rev.1.00 Sep. 18, 2008 Page 113 of 522

REJ09B0069-0100

7.10

On-chip Peripheral I/O Register Access

Internal I/O registers are accessed from the bus state controller, as shown in table 7.3.

Table 7.3

Access to Internal I/O Registers

Internal Module

SCI

MTU,

POE

INTC

PFC,

PORT

CMT

A/D

WDT

MMT

Connected bus

width

8 bits

16 bits

8 bits

16 bits

Access cycles

2 cyc*

3 cyc*

2 cyc*

Notes: 1. Converted to the peripheral clock.

2. Converted to the system clock.

7.11

Cycles in which Bus Is not Released

One Bus Cycle: The bus is never released during a single bus cycle. For example, in the case of a

longword read (or write) in 8-bit normal space, four memory accesses to the 8-bit normal space

constitute a single bus cycle, and the bus is never released during this period. Assuming that one

memory access requires two states, the bus is not released during an 8-state period.

8 bits

Cycles in which

bus is not released

Figure 7.10 One Bus Cycle

7.12

CPU Operation when Program Is in External Memory

In this LSI, two words (equivalent to two instructions) are normally fetched in a single instruction

fetch. This is also true when the program is located in external memory, irrespective of whether

the external memory bus width is 8 or 16 bits.

If the program counter value immediately after the program branched is an odd-word (2n+1)

address, or if the program counter value immediately before the program branches is an even-word

(2n) address, the CPU will always fetch 32 bits (equivalent to two instructions) that include the

respective word instruction.

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