SH7101 datasheet(185/560 Pages) RENESAS

185 / 560 page

Section 8 Multifunction Timer Pulse Unit (MTU)

Rev.1.00 Sep. 18, 2008 Page 151 of 522

REJ09B0069-0100

8.3.9

Timer Synchro Register (TSYR)

TSYR is an 8-bit readable/writable register that selects independent operation or synchronous

operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when

the corresponding bit in TSYR is set to 1.

Bit

Bit Name

Initial

value

R/W

Description

SYNC4

SYNC3

R/W

Timer Synchro 4 and 3

These bits are used to select whether operation is

independent of or synchronized with other channels.

When synchronous operation is selected, the TCNT

synchronous presetting of multiple channels, and

synchronous clearing by counter clearing on another

channel, are possible.

To set synchronous operation, the SYNC bits for at least

two channels must be set to 1. To set synchronous

clearing, in addition to the SYNC bit, the TCNT clearing

source must also be set by means of bits CCLR0 to

CCLR2 in TCR.

0: TCNT_4 and TCNT_3 operate independently (TCNT

presetting/clearing is unrelated to other channels)

1: TCNT_4 and TCNT_3 performs synchronous

operation

TCNT synchronous presetting/synchronous clearing is

possible

5 to 3 —

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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