SH7101 datasheet(242/560 Pages) RENESAS

242 / 560 page

Section 8 Multifunction Timer Pulse Unit (MTU)

Rev.1.00 Sep. 18, 2008 Page 208 of 522

REJ09B0069-0100

A/D Conversion Start Request Setting: In complementary PWM mode, an A/D conversion start

request can be set using a TGRA_3 compare-match or a compare-match on a channel other than

channels 3 and 4.

When start requests using a TGRA_3 compare-match are set, A/D conversion can be started at the

center of the PWM pulse.

A/D conversion start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable

Complementary PWM Mode Output Protection Function

Complementary PWM mode output has the following protection functions.

• Register and counter miswrite prevention function

With the exception of the buffer registers, which can be rewritten at any time, access by the

CPU can be enabled or disabled for the mode registers, control registers, compare registers,

and counters used in complementary PWM mode by means of bit 13 in the bus controller’s bus

control register 1 (BCR1). The registers and counters concerned are listed in table 8.3.

This function enables the CPU to prevent miswriting due to CPU runaway by disabling CPU

access to the mode registers, control registers, and counters.

• Halting of PWM output by external signal

The 6-phase PWM output pins can be set automatically to the high-impedance state by

inputting specified external signals. There are four external signal input pins.

See section 8.9, Port Output Enable (POE), for details.

• Halting of PWM output when oscillator is stopped

If it is detected that the clock input to this LSI has stopped, the 6-phase PWM output pins

automatically go to the high-impedance state. The pin states are not guaranteed when the clock

is restarted.

For details, see section 4.2, Function for Detecting the Oscillator Halt.

SH7101 Datasheet(PDF) 242 Page - Renesas Technology Corp