SH7101 datasheet(245/560 Pages) RENESAS

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Section 8 Multifunction Timer Pulse Unit (MTU)

Rev.1.00 Sep. 18, 2008 Page 211 of 522

REJ09B0069-0100

Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the

TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt

request is cleared by clearing the TCFV flag to 0. The MTU has five overflow interrupts, one for

each channel.

Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the

TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt

request is cleared by clearing the TCFU flag to 0. The MTU has four underflow interrupts, one

each for channels 1 and 2.

8.5.2

A/D Converter Activation

The A/D converter can be activated by the TGRA input capture/compare match in each channel.

If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a

TGRA input capture/compare match on a particular channel, a request to start A/D conversion is

sent to the A/D converter. If the MTU conversion start trigger has been selected on the A/D

converter at this time, A/D conversion starts.

In the MTU, a total of five TGRA input capture/compare match interrupts can be used as A/D

converter conversion start sources, one for each channel.

8.6

Operation Timing

8.6.1

Input/Output Timing

TCNT Count Timing: Figure 8.54 shows TCNT count timing in internal clock operation, and

Figure 8.55 shows TCNT count timing in external clock operation (normal mode), and figure 8.56

shows TCNT count timing in external clock operation (phase counting mode).

TCNT

TCNT input

clock

Internal clock

N-1

N+1

N+2

Falling edge

Rising edge

Figure 8.54 Count Timing in Internal Clock Operation

SH7101 Datasheet(PDF) 245 Page - Renesas Technology Corp