SH7785 datasheet(131/1692 Pages) RENESAS

131 / 1692 page

5. Exception Handling

Rev.1.00 Jan. 10, 2008 Page 101 of 1658

REJ09B0261-0100

5.5.3

Exception Requests and BL Bit

When the BL bit in SR is 0, general exceptions and interrupts are accepted.

When the BL bit in SR is 1 and an general exception other than a user break is generated, the

CPU's internal registers and the registers of the other modules are set to their states following a

manual reset, and the CPU branches to the same address as in a reset (H'A0000000). For the

operation in the event of a user break, see section 29, User Break Controller (UBC). If an ordinary

interrupt occurs, the interrupt request is held pending and is accepted after the BL bit has been

cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held pending or

accepted according to the setting made by software. For further details, refer to the hardware

manual of the product.

Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, to enable

multiple exception state acceptance.

5.5.4

Return from Exception Handling

The RTE instruction is used to return from exception handling. When the RTE instruction is

executed, the SPC contents are restored to PC and the SSR contents to SR, and the CPU returns

from the exception handling routine by branching to the SPC address. If SPC and SSR were saved

to external memory, set the BL bit in SR to 1 before restoring the SPC and SSR contents and

issuing the RTE instruction.

SH7785 Datasheet(PDF) 131 Page - Renesas Technology Corp