SH7785 datasheet(159/1692 Pages) RENESAS

159 / 1692 page

6. Floating-Point Unit (FPU)

Rev.1.00 Jan. 10, 2008 Page 129 of 1658

REJ09B0261-0100

6.2.2

Non-Numbers (NaN)

Figure 6.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case:

• Sign bit: Don't care

• Exponent field: All bits are 1

• Fraction field: At least one bit is 1

The NaN is a signaling NaN (sNaN) if the MSB of the fraction field is 1, and a quiet NaN (qNaN)

if the MSB is 0.

31 30

23 22

N = 1:sNaN

N = 0:qNaN

11111111

Nxxxxxxxxxxxxxxxxxxxxxx

Figure 6.3 Single-Precision NaN Bit Pattern

An sNaN is assumed to be the input data in an operation, except the transfer instructions between

registers, FABS, and FNEG, that generates a floating-point value.

• When the EN.V bit in FPSCR is 0, the operation result (output) is a qNaN.

• When the EN.V bit in FPSCR is 1, an invalid operation exception will be generated. In this

case, the contents of the operation destination register are unchanged.

Following three instructions are used as transfer instructions between registers.

• FMOV FRm,FRn

• FLDS FRm,FPUL

• FSTS FPUL,FRn

If a qNaN is input in an operation that generates a floating-point value, and an sNaN has not been

input in that operation, the output will always be a qNaN irrespective of the setting of the EN.V bit

in FPSCR. An exception will not be generated in this case.

The qNAN values as operation results are as follows:

• Single-precision qNaN: H'7FBF FFFF

• Double-precision qNaN: H'7FF7 FFFF FFFF FFFF

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