SH7785 datasheet(163/1692 Pages) RENESAS

163 / 1692 page

6. Floating-Point Unit (FPU)

Rev.1.00 Jan. 10, 2008 Page 133 of 1658

REJ09B0261-0100

6.3.2

Floating-Point Status/Control Register (FPSCR)

bit:

0000000000000100

Initial value:

RRRRRRRRRR

R/W

R/W:

bit:

0000000000000001

Initial value:

R/W

R/W:

Enable (EN)

Flag

Cause

Bit

Bit Name

Initial

Value

R/W

Description

31 to 22 —

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

R/W

Floating-Point Register Bank

0: FPR0_BANK0 to FPR15_BANK0 are assigned to

FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1

are assigned to XF0 to XF15

1: FPR0_BANK0 to FPR15_BANK0 are assigned to

XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1

are assigned to FR0 to FR15

R/W

Transfer Size Mode

0: Data size of FMOV instruction is 32-bits

1: Data size of FMOV instruction is a 32-bit register

pair (64 bits)

For relations between endian and the SZ and PR bits,

see figure 6.5.

R/W

Precision Mode

0: Floating-point instructions are executed as

single-precision operations

1: Floating-point instructions are executed as

double-precision operations (graphics support

instructions are undefined)

For relations between endian and the SZ and PR bits,

see figure 6.5.

R/W

Denormalization Mode

0: Denormalized number is treated as such

1: Denormalized number is treated as zero

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