SH7785 datasheet(167/1692 Pages) RENESAS

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6. Floating-Point Unit (FPU)

Rev.1.00 Jan. 10, 2008 Page 137 of 1658

REJ09B0261-0100

6.4

Rounding

In a floating-point instruction, rounding is performed when generating the final operation result

from the intermediate result. Therefore, the result of combination instructions such as FMAC,

FTRV, and FIPR will differ from the result when using a basic instruction such as FADD, FSUB,

or FMUL. Rounding is performed once in FMAC, but twice in FADD, FSUB, and FMUL.

Which of the two rounding methods is to be used is determined by the RM bits in FPSCR.

FPSCR.RM[1:0] = 00: Round to Nearest

FPSCR.RM[1:0] = 01: Round to Zero

(1)

Round to Nearest

The operation result is rounded to the nearest expressible value. If there are two nearest

expressible values, the one with an LSB of 0 is selected.

If the unrounded value is 2

Emax (2 – 2–P) or more, the result will be infinity with the same sign as the

unrounded value. The values of Emax and P, respectively, are 127 and 24 for single-precision, and

1023 and 53 for double-precision.

(2)

Round to Zero

The digits below the round bit of the unrounded value are discarded.

If the unrounded value is larger than the maximum expressible absolute value, the value will

become the maximum expressible absolute value with the same sign as unrounded value.

SH7785 Datasheet(PDF) 167 Page - Renesas Technology Corp