SH7785 datasheet(170/1692 Pages) RENESAS

170 / 1692 page

6. Floating-Point Unit (FPU)

Rev.1.00 Jan. 10, 2008 Page 140 of 1658

REJ09B0261-0100

6.6

Graphics Support Functions

This LSI supports two kinds of graphics functions: new instructions for geometric operations, and

pair single-precision transfer instructions that enable high-speed data transfer.

6.6.1

Geometric Operation Instructions

Geometric operation instructions perform approximate-value computations. To enable high-speed

computation with a minimum of hardware, this LSI ignores comparatively small values in the

partial computation results of four multiplications. Consequently, the error shown below is

produced in the result of the computation:

Maximum error = MAX (individual multiplication result

–MIN (number of multiplier significant digits–1, number of multiplicand significant digits–1)) + MAX (result value

× 2–23, 2–149)

The number of significant digits is 24 for a normalized number and 23 for a denormalized number

(number of leading zeros in the fractional part).

In a future version of the SH Series, the above error is guaranteed, but the same result between

different processor cores is not guaranteed.

(1)

FIPR FVm, FVn (m, n: 0, 4, 8, 12)

This instruction is basically used for the following purposes:

• Inner product (m ≠ n):

This operation is generally used for surface/rear surface determination for polygon surfaces.

• Sum of square of elements (m = n):

This operation is generally used to find the length of a vector.

Since an inexact exception is not detected by an FIPR instruction, the inexact exception (I) bit in

both the FPU exception cause field and flag field are always set to 1 when an FIPR instruction is

executed. Therefore, if the I bit is set in the FPU exception enable field, FPU exception handling

will be executed.

SH7785 Datasheet(PDF) 170 Page - Renesas Technology Corp