32186 datasheet(643/1032 Pages) RENESAS

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CAN MODULE

13-33

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

(1) SJW bits (Bits 0–1)

These bits set the reSynchronization Jump Width.

(2) PH2 bits (Bits 2–4)

These bits set the width of Phase Segment2.

(3) PH1 bits (Bits 5–7)

These bits set the width of Phase Segment1.

(4) PRB bits (Bits 8–10)

These bits set the width of Propagation Segment.

(5) SAM bit (Bit 11)

This bit sets the number of times each bit is sampled. When SAM = "0," the value sampled at the end of

Phase Segment1 is assumed to be the value of the bit. When SAM = "1," the value of the bit is determined

by a majority circuit from three sampled values, each sampled 2 Tq’s before, 1 Tq before, and at the end of

Phase Segment1.

Table 13.2.1 Typical Settings of Bit Timing when CAN module clock = 20 MHz (Note 2)

Baud Rate

BRP Set Value

Tq Period (ns)

No. of Tq’s in 1 Bit

PROP + PH1

PH2

bit timing

1000K bps

100

90%

80%

70%

60%

500K bps

100

90% (Note 1)

85% (Note 1)

80% (Note 1)

75% (Note 1)

70%

65%

60%

200

90%

80%

70%

60%

250

87.5%

75%

62.5%

Note 1: PH2 = max (PH1, IPT), that is specified in CAN protocol, cannot be met.

Note 2: As for Can module clock, select CPUCLK/4 in CAN Clock Select Register.

Note: • It does not mean that the communication at the above baud rate settings is guaranteed. Sufficient evaluation and

verification are required before use.

13.2 CAN Module Related Registers

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