32186 datasheet(162/1032 Pages) RENESAS

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INTERNAL MEMORY

6-20

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

6.5 Registers Associated with Internal Flash Memory

(2) FPBSYCK (Prebusy Check) bit (Bit 7)

The FPBSYCK bit is used to check whether the command of two or more cycles (confirmation command

H'D0D0 or a command that requires write data) issued to the flash memory during flash E/W enable mode

has been accepted normally. If the FPBSYCK bit is found to be "0" after issuing the prebusy check target

command (See Table 6.5.2), it means that the prebusy check target command has been accepted normally.

Conversely, if the FPBSYCK bit is found to be "1," it means that the prebusy check target command has not

been accepted normally.

In addition to the above, the FPBSYCK bit is set to "1" in the following cases:

1) When in a ready state (FBUSY bit = "H" after a prebusy check target command has been accepted)

2) When the Clear Status Register command is issued

3) When the FRESET bit = "1"

4) When input on RESET# pin is pulled "L"

Table 6.5.2 Prebusy, Busy Check Target Comand

(Note1)

(Note2)

(Note1)

(Note2)

(Note1)

(Note2)

(Note1)

(Note2)

Lock bit Program

Write H'7777

(Lock bit program

command)

Write H'2020

(Block erase command)

Write H'7171

(Read lock bit status

command)

Write H'4343

(4 halfword program

command)

Write H'D0D0

(Confirmation command)

Write H'D0D0

(Confirmation command)

Write H'D0D0

(Confirmation command)

Write halfword data

Block Erase

Read Lock bit Status

(during Register read mode)

4 Halfword Program

Note 1: Prebusy check target command

Note 2: Busy check target command

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