32192 datasheet(55/1044 Pages) RENESAS

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2-11

32192/32195/32196 Group Hardware Manual

Rev.1.10 REJ09B0123-0110 Apr.06.07

CPU

• Constant transfer

LD24

Rdest, #imm24

LDI

Rdest, #imm16

LDI

Rdest, #imm8

SETH

Rdest, #imm16

b23

Rdest

imm24

b31

LD24

Rdest, #imm24

b15

Rdest

imm16

b31

SETH

Rdest, #imm16

• Register to register transfer

Rdest, Rsrc

• Control register transfer

MVFC Rdest, CRsrc

MVTC Rsrc, CRdest

Rsrc

b31

Rdest

b31

Rsrc

b31

CRdest

b31

MVTC Rsrc, CRdest

Rdest, Rsrc

Note: • The condition bit C changes state when data is written to CR0 (PSW) using the MVTC instruction.

Figure 2.6.6 Transfer Instructions

Little/little

Big/big

Little/big

Endian

(bit/byte)

Data arrangement

Microcomputer

family name

7700 and M16C Families

M32R Family

31–24

7–0

23–16

15–8

0–7

24–31

8–15

16–23

Bit number

Address

Example:

0x01234567

.byte 67,45,23,01

.byte 01,23,45,67

Note: • The M32R Family uses the big endian for both bits and bytes.

7–0

31–24

15–8

23–16

Figure 2.6.5 Endian Adopted for the M32R Family

(4) Transfer instructions

2.6 Data Formats

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