32192 datasheet(27/1044 Pages) RENESAS

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1-7

OVERVIEW

32192/32195/32196 Group Hardware Manual

Rev.1.10 REJ09B0123-0110 Apr.06.07

1.2 Block Diagram

Table 1.2.1 Features of the 32192/32195/32196 (1/3)

Functional Block

Features

M32R-FPU CPU core

• Implementation: Six-stage pipelined instruction processing

• Internal 32-bit structure of the core

• Register configuration

General-purpose registers: 32 bits × 16 registers

Control registers: 32 bits × 6 registers

• Instruction set

16-bit and 32-bit instruction formats

100 discrete instructions and six addressing modes

• Internal multiplier/accumulator (32 bits × 16 bits + 56 bits)

• Internal single-precision floating-point arithmetic unit (FPU)

Internal Flash memory

• Capacity:

M32192F8 : 1 Mbyte

M32195F4 : 512 Kbytes

M32196F8 : 1 Mbyte

• One wait access

• Durability: Rewritable 100 times

Internal RAM

• Capacity:

M32192F8 : 176 Kbytes

M32195F4 : 32 Kbytes

M32196F8 : 64 Kbytes

•Zero wait access

• The internal RAM can be accessed for reading or rewriting data from the outside independently of the

M32R-FPU by using the Real-Time Debugger, without ever causing the CPU performance to decrease.

• By using RAM backup mode, a part of internal RAM area can be backed up when turn off the power supply.

Bus specification

• Fundamental bus cycle : 6.25 ns (when f(CPUCLK) = 160 MHz)

• Logical address space : 4 Gbytes linear

• Internal bus specification : Internal 32-bit data bus (for CPU <-> internal flash memory and RAM access)

(or accessed in 64 bits when accessing the internal flash memory for instructions)

: Internal 16-bit data bus (for internal peripheral I/O access)

• External extension area: During processor mode: maximum 32 Mbytes

During external extension mode: maximum 31 Mbytes

(7 Mbytes + 8 Mbytes × 3 blocks)

• External data address: 22-bit address

• External data bus: 16-bit data bus

• Shortest external bus access: 1 CLKOUT during read, 1 CLKOUT during write

Multijunction timer (MJT)

• 55-channel multi-functional timer

16-bit output related timer × 11 channels, 16-bit input/output related timer × 10 channels,

16-bit input related timer × 8 channels, 32-bit input related timer × 8 channels,

16-bit input related up/down timer × 2 channels, and 24-bit output related timer × 16 channels

• Flexible timer configuration is possible by interconnecting these timer channels.

• Interrupt request: Counter underflow or overflow and rising or falling or both edges or “H” or “L” level

from the TIN pin (TIN pin can be used as external interrupt inputs irrespective of timer operation.)

• DMA transfer request: Counter underflow or overflow and rising or falling or both edges or “H” or

“L” level from the TIN pin (TIN pin can be used as DMA transfer request inputs irrespective of

timer operation.)

DMAC

• Number of channels: 10

• Transfers between internal peripheral I/Os or internal RAMs or between internal peripheral I/O

and internal RAM are supported.

• Capable of advanced DMA transfers when used in combination with internal peripheral I/O

• Transfer request: Software or internal peripheral I/O (A/D converter, MJT, serial interface or CAN)

• DMA channels can be cascaded. (DMA transfer on a channel can be started by completion of a

transfer on another channel.)

• Interrupt request: DMA transfer counter register underflow

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