32192 datasheet(26/1044 Pages) RENESAS

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1-6

32192/32195/32196 Group Hardware Manual

OVERVIEW

Rev.1.10 REJ09B0123-0110 Apr.06.07

1.2 Block Diagram

Figure 1.2.1 shows a block diagram of the 32192/32195/32196. The features of each block are described in

Table 1.2.1.

Figure 1.2.1 Block Diagram of the 32192/32195/32196

M32R-FPU Core

(Max. 160MHz)

Non-Break Debug

(NBD)

Direct RAM

Interface

(DRI)

Multiplier/Accumulator

(32 bits x 16 bits + 56 bits)

Single-precision FPU

(fully IEEE 754 compliant)

Internal Flash Memory

(M32192F8: 1 Mbyte)

(M32195F4: 512 Kbytes)

(M32196F8: 1 Mbyte)

Internal RAM

(M32192F8: 176 Kbytes)

(M32195F4: 32 Kbytes)

(M32196F8: 64 Kbytes)

PLL Clock Generator

Internal Power Supply

Generator (VDC)

Address

Data

External Bus

Interface

Input/output ports, 97 lines

Real-Time

Debugger

(RTD)

Internal Bus

Interface

DMAC

(10 channels)

Multijunction Timer

(MJT: 55 channels)

A/D Converter

(A/D0: 10-bit converter, 16 channels)

Serial Interface

(6 channels)

Interrupt Controller

(8 levels)

Wait Controller

Full CAN

(2 channels)

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