32192 datasheet(15/1044 Pages) RENESAS

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Contents-9

32192/32195/32196 Group Hardware Manual

Rev.1.10 REJ09B0123-0110 Apr.06.07

CHAPTER 14 DIRECT RAM INTERFACE (DRI)

14.1 Outline of the Direct RAM Interface (DRI) --------------------------------------------------------------------------- 14-2

14.2 DRI Related Registers -------------------------------------------------------------------------------------------------- 14-4

14.2.1

DD Input Pin Select Register -------------------------------------------------------------------------------- 14-6

14.2.2

DRI Interrupt Related Registers ----------------------------------------------------------------------------- 14-7

14.2.3

DRI Transfer Control Register ------------------------------------------------------------------------------- 14-13

14.2.4

DRI Special Mode Control Register ------------------------------------------------------------------------ 14-15

14.2.5

DRI Data Capture Control Register ------------------------------------------------------------------------ 14-18

14.2.6

DRI Data Interleave Control Register ---------------------------------------------------------------------- 14-22

14.2.7

DD Input Event Select Register ----------------------------------------------------------------------------- 14-22

14.2.8

DD Input Enable Registers ---------------------------------------------------------------------------------- 14-23

14.2.9

DRI Data Capture Event Count Setting Register -------------------------------------------------------- 14-25

14.2.10

DRI Capture Event Counter ---------------------------------------------------------------------------------- 14-26

14.2.11

DRI Transfer Counter ------------------------------------------------------------------------------------------ 14-27

14.2.12

DRI Address Counters ---------------------------------------------------------------------------------------- 14-28

14.2.13

DRI Address Reload Registers ----------------------------------------------------------------------------- 14-29

14.2.14

DIN Input Processing Control Register ------------------------------------------------------------------- 14-30

14.2.15

DRI Event Counter (DEC) Control Registers ------------------------------------------------------------- 14-31

14.2.16

DRI Event Counters (DEC Counters) ---------------------------------------------------------------------- 14-36

14.2.17

DRI Event Counter (DEC) Reload Registers ------------------------------------------------------------- 14-36

14.3 Notes on DRI -------------------------------------------------------------------------------------------------------------- 14-37

CHAPTER 15 REAL TIME DEBUGGER (RTD)

15.1 Outline of the Real-Time Debugger (RTD) -------------------------------------------------------------------------- 15-2

15.2 Pin Functions of the RTD ----------------------------------------------------------------------------------------------- 15-3

15.3 RTD Related Register --------------------------------------------------------------------------------------------------- 15-3

15.3.1

RTD Write Function Disable Register --------------------------------------------------------------------- 15-3

15.4 Functional Description of the RTD ------------------------------------------------------------------------------------ 15-4

15.4.1

Outline of the RTD Operation -------------------------------------------------------------------------------- 15-4

15.4.2

Operation of RDR (Real-time RAM Content Output) --------------------------------------------------- 15-4

15.4.3

Operation of the WRR (RAM Content Forcible Rewrite) ---------------------------------------------- 15-6

15.4.4

Operation of VER (Continuous Monitor) ------------------------------------------------------------------ 15-7

15.4.5

Operation of VEI (Interrupt Request) ----------------------------------------------------------------------- 15-7

15.4.6

Operation of RCV (Recover from Runaway) -------------------------------------------------------------- 15-8

15.4.7

Method for Setting a Specified Address when Using the RTD -------------------------------------- 15-9

15.4.8

Resetting the RTD --------------------------------------------------------------------------------------------- 15-10

15.5 Typical Connection with the Host ------------------------------------------------------------------------------------- 15-11

CHAPTER 16 NON-BREAK DEBUG (NBD)

16.1 Outline of the Non-Break Debug (NBD) ----------------------------------------------------------------------------- 16-2

16.2 Pin Functions of NBD --------------------------------------------------------------------------------------------------- 16-4

16.2.1

NBD Pin Control Register ------------------------------------------------------------------------------------ 16-4

16.3 NBD Related Registers ------------------------------------------------------------------------------------------------- 16-6

16.3.1

NBD Enable Register ----------------------------------------------------------------------------------------- 16-6

16.4 Communication Protocol ----------------------------------------------------------------------------------------------- 16-7

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