32192 datasheet(10/1044 Pages) RENESAS

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Contents-4

32192/32195/32196 Group Hardware Manual

Rev.1.10 REJ09B0123-0110 Apr.06.07

CHAPTER 9 DMAC

9.1 Outline of the DMAC ------------------------------------------------------------------------------------------------------ 9-2

9.2 DMAC Related Registers ------------------------------------------------------------------------------------------------ 9-4

9.2.1

DMA Channel Control Registers ---------------------------------------------------------------------------- 9-6

9.2.2

DMA Software Request Generation Registers ----------------------------------------------------------- 9-29

9.2.3

DMA Source Address Registers ---------------------------------------------------------------------------- 9-30

9.2.4

DMA Destination Address Registers ----------------------------------------------------------------------- 9-31

9.2.5

DMA Transfer Count Registers ------------------------------------------------------------------------------ 9-32

9.2.6

DMA Interrupt Related Registers ---------------------------------------------------------------------------- 9-33

9.3 Functional Description of the DMAC ---------------------------------------------------------------------------------- 9-38

9.3.1

DMA Transfer Request Sources ----------------------------------------------------------------------------- 9-38

9.3.2

DMA Transfer Processing Procedure ---------------------------------------------------------------------- 9-44

9.3.3

Starting DMA ---------------------------------------------------------------------------------------------------- 9-45

9.3.4

DMA Channel Priority ------------------------------------------------------------------------------------------ 9-45

9.3.5

Gaining and Releasing Control of the Internal Bus ------------------------------------------------------ 9-45

9.3.6

Transfer Units ---------------------------------------------------------------------------------------------------- 9-46

9.3.7

Transfer Counts ------------------------------------------------------------------------------------------------- 9-46

9.3.8

Address Space -------------------------------------------------------------------------------------------------- 9-46

9.3.9

Transfer Operation --------------------------------------------------------------------------------------------- 9-46

9.3.10

End of DMA and Interrupt ------------------------------------------------------------------------------------- 9-48

9.3.11

Each Register Status after Completion of DMA Transfer ---------------------------------------------- 9-48

9.4 Notes on the DMAC ------------------------------------------------------------------------------------------------------- 9-49

CHAPTER 10 MULTIJUNCTION TIMERS

10.1 Outline of Multijunction Timers ---------------------------------------------------------------------------------------- 10-2

10.2 Common Units of Multijunction Timers ------------------------------------------------------------------------------ 10-9

10.2.1

MJT Common Unit Register Map --------------------------------------------------------------------------- 10-10

10.2.2

Common Count Clock Select Function ------------------------------------------------------------------- 10-12

10.2.3

Prescaler Unit --------------------------------------------------------------------------------------------------- 10-13

10.2.4

Clock Bus and Input/Output Event Bus Control Unit -------------------------------------------------- 10-14

10.2.5

Input Processing Control Unit ------------------------------------------------------------------------------- 10-18

10.2.6

Output Flip-flop Control Unit --------------------------------------------------------------------------------- 10-26

10.2.7

Interrupt Control Unit ------------------------------------------------------------------------------------------ 10-34

10.3 TOP (Output-Related 16-Bit Timer) ----------------------------------------------------------------------------------- 10-60

10.3.1

Outline of TOP --------------------------------------------------------------------------------------------------- 10-60

10.3.2

Outline of Each Mode of TOP -------------------------------------------------------------------------------- 10-62

10.3.3

TOP Related Register Map ----------------------------------------------------------------------------------- 10-64

10.3.4

TOP Control Registers ----------------------------------------------------------------------------------------- 10-66

10.3.5

TOP Counters (TOP0CT–TOP10CT) ----------------------------------------------------------------------- 10-71

10.3.6

TOP Reload Registers (TOP0RL–TOP10RL) ------------------------------------------------------------- 10-72

10.3.7

TOP Correction Registers (TOP0CC–TOP10CC) -------------------------------------------------------- 10-73

10.3.8

TOP Enable Control Registers ------------------------------------------------------------------------------- 10-74

10.3.9

Operation in TOP Single-shot Output Mode (with Correction Function) ---------------------------- 10-76

10.3.10

Operation in TOP Delayed Single-shot Output Mode (with Correction Function) ---------------- 10-82

10.3.11

Operation in TOP Continuous Output Mode (without Correction Function) ------------------------ 10-87

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