32192 datasheet(25/1044 Pages) RENESAS

25 / 1044 page

1-5

OVERVIEW

32192/32195/32196 Group Hardware Manual

Rev.1.10 REJ09B0123-0110 Apr.06.07

1.1 Outline of the 32192/32195/32196 Group

1.1.5 Built-in Clock Frequency Multiplier

• The 32192/32195/32196 contains a clock frequency multiplier, which is schematically shown in Figure 1.1.1

below.

1/4

PLL

1/2

CLKO

SEL

CLKOUT(external bus clock)

(32MHz-40MHz or 16MHz-20MHz)

XIN pin

(16MHz-20MHz)

BCLK (peripheral clock)

(32MHz-40MHz)

CPUCLK (CPU clock)

(128MHz-160MHz)

Figure 1.1.1 Conceptual Diagram of the Clock Frequency Multiplier

Table 1.1.2 Clock

Functional Block

Features

CPUCLK

• CPU clock: Defined as f(CPUCLK) when it indicates the operating clock frequency for

the M32R-FPU core, internal flash memory and internal RAM.

BCLK

• Peripheral clock: Defined as f(BCLK) when it indicates the operating clock frequency for

the internal peripheral I/O and external data bus.

Clock output

• BCLK pin output: A clock with the same frequency as f(BCLK) is output from this pin.

• CLKOUT pin output: A clock with the same or half frequency as f(BCLK) is output from this pin.

1.1.6 Powerful Peripheral Functions Built-in

(1) 8-level interrupt controller (ICU)

(2) 10-channel DMAC

(3) 55-channel multijunction timer (MJT)

(4) 16-channel A/D converter (ADC)

(5) 6-channel serial interface (SIO)

(6) 2-channel Full-CAN

(7) Direct RAM interface (DRI)

(8) Real-time debugger (RTD)

(9) Non-break debug (NBD)

(10) Wait controller

(11) M32R Family’s common debug function (Scalable Debug Interface or SDI)

32192 Datasheet(PDF) 25 Page - Renesas Technology Corp

32192 Datasheet(HTML) 25 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL