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SH7021 Datasheet(PDF) 36 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 36 Page - Renesas Technology Corp |
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36 / 509 page ![]() RENESAS15 Section 2 CPU 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers (Rn) General registers Rn consist of sixteen 32-bit registers (R0–R15). General registers are used for data processing and address calculation. Register R0 also functions as an index register. For some instructions, the R0 register must be used. Register R15 functions as a stack pointer to save or recover status registers (SR) and program counter (PC) during exception processing. R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP 0 31 R0 functions as an index register in the indexed register addressing mode and indirect indexed GBR addressing mode. In some instruc- tions, R0 functions as a source register or a destination register. R15 functions as a stack pointer (SP) during exception processing. Figure 2.1 General Registers (Rn) 2.1.2 Control Registers Control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register |
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