SH7021 datasheet(70/509 Pages) RENESAS

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Table 4.2 lists vector numbers and vector table address offsets. Table 4.3 shows how to calculate

vector table addresses.

Table 4.2

Exception Process Vector Table

Exception Source

Vector

Number

Vector table Address Offset

Power-on reset

H'00000000–H'00000003

H'00000004–H'00000007

Manual reset

H'00000008–H'0000000B

H'0000000C–H'0000000F

General illegal instruction

H'00000010–H'00000013

(Reserved for system use)

H'00000014–H'00000017

Illegal slot instruction

H'00000018–H'0000001B

(Reserved for system use)

H'0000001C–H'0000001F

H'00000020–H'00000023

CPU address error

H'00000024–H'00000027

DMA address error

H'00000028–H'0000002B

Interrupts

NMI

H'0000002C–H'0000002F

User

break

H'00000030–H'00000033

(Reserved for system use)

13–31

H'00000034–H'00000037 to H'0000007C–

H'0000007F

Trap instruction (user

vectors)

32–63

H'00000080–H'00000083 to H'000000FC–

H'000000FF

Interrupts

IRQ0

H'00000100–H'00000103

IRQ1

H'00000104–H'00000107

IRQ2

H'00000108–H'0000010B

IRQ3

H'0000010C–H'0000010F

IRQ4

H'00000110–H'00000113

IRQ5

H'00000114–H'00000117

IRQ6

H'00000118–H'0000011B

IRQ7

H'0000011C–H'0000011F

On-chip

modules*

72–255

H'00000120–H'00000123 to H'000003FC–

H'000003FF

Note:

See table 5.3, Interrupt Exception Processing Vectors and Rankings, in section 5, Interrupt

Controller, for details on vector numbers and vector table address offsets of individual on-

chip peripheral module interrupts.

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