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2.3

Instruction Features

2.3.1

RISC-Type Instruction Set

All instructions are RISC type. Their features are as follows:

16-Bit Fixed Length: Every instruction is 16 bits long, making program coding much more

efficient.

One Instruction/Cycle: Basic instructions can be executed in one cycle using the pipeline system.

One-cycle instructions are executed in 50 ns at 20 MHz.

Data Length: Long word is the standard data length for all operations. Memory can be accessed

in bytes, words, or long words. Byte or word data accessed from memory is sign-extended and

handled as long word data. Immediate data is sign-extended for arithmetic operations or zero-

extended for logic operations (handled as long word data).

Table 2.2

Sign Extension of Word Data

CPU of SH7000 Series

Description

Conventional CPUs

MOV.W

@(disp,PC),R1

ADD

R1,R0

......................

.DATA.W

H'1234

Data is sign-extended to 32 bits, and

R1 becomes H'00001234. It is next

operated upon by an ADD instruction.

ADD.W #H'1234, R0

Note:

The address of the immediate data is accessed by @(disp, PC).

Load-Store Architecture: Basic operations are executed between registers. For operations that

involve memory, data is loaded to the registers and executed (load-store architecture). Instructions

such as AND that manipulate bits, however, are executed directly in memory.

Delayed Branch Instructions: Unconditional branch instructions are delayed. Pipeline disruption

during branching is reduced by first executing the instruction that follows the branch instruction,

and then branching. See the SH-1/SH-2 Programming Manual for details.

Table 2.3

Delayed Branch Instructions

CPU of SH7000 Series

Description

Conventional CPU

BRA

TRGET

ADD

R1, R0

Executes an ADD before

branching to TRGET.

ADD.W

R1, R0

BRA

TRGET

Multiplication/Accumulation Operation: The five-stage pipeline system and the on-chip

multiplier enable 16-bit

× 16-bit → 32-bit multiplication operations to be executed in 1–3 cycles.

16-bit

× 16-bit + 42-bit → 42-bit multiplication/accumulation operations can be executed in 2–3

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