SH7021 datasheet(83/509 Pages) RENESAS

83 / 509 page

64 RENESAS

5.2.1

NMI Interrupts

NMI is the highest-priority interrupt (level 16) and is always accepted. Input at the NMI pin is

edge-sensed. Either the rising or falling edge can be selected by setting the NMI edge select bit

(NMIE) in the interrupt control register (ICR). NMI interrupt exception processing sets the

interrupt mask level bits (I3–I0) in the status register (SR) to level 15.

5.2.2

User Break Interrupt

A user break interrupt occurs when a break condition is satisfied in the user break controller

(UBC). A user break interrupt has priority level 15. User break interrupt exception processing sets

the interrupt mask level bits (I3–I0) in the status register (SR) to level 15. For further details about

the user break interrupt, see section 6, User Break Controller.

5.2.3

IRQ Interrupts

IRQ interrupts are requested by input from pins

IRQ0-IRQ7. IRQ sense select bits 0–7 (IRQ0S–

IRQ7S) in the interrupt control register (ICR) can select low-level sensing or falling-edge sensing

for each pin independently. Interrupt priority registers A and B (IPRA and IPRB) can select

priority levels from 0–15 for each pin. IRQ interrupt exception processing sets the interrupt mask

level bits (I3–I0) in the status register (SR) to the priority level value of the IRQ interrupt that was

accepted.

5.2.4

On-Chip Interrupts

On-chip interrupts are interrupts generated by the following 5 on-chip peripheral modules:

•

Direct memory access controller (DMAC)

•

16-bit integrated-timer pulse unit (ITU)

•

Serial communications interface (SCI)

•

Bus state controller (BSC)

•

Watchdog timer (WDT)

A different interrupt vector is assigned to each interrupt source, so the exception service routine

does not have to decide which interrupt has occurred. Priority levels 0–15 can be assigned to

individual on-chip peripheral module in interrupt priority registers C–E (IPRC–IPRE). On-chip

interrupt exception processing sets the interrupt mask level bits (I3–I0) in the status register (SR)

to the priority level value of the on-chip interrupt that was accepted.

SH7021 Datasheet(PDF) 83 Page - Renesas Technology Corp