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Table 2.15

Shift Instructions

Instruction

Instruction Code

Operation

Execution Cycles

T bit

ROTL

0100nnnn00000100

← Rn ← MSB

MSB

ROTR

0100nnnn00000101

LSB

→ Rn → T

LSB

ROTCL

0100nnnn00100100

← Rn ← T

MSB

ROTCR

0100nnnn00100101

→ Rn → T

LSB

SHAL

0100nnnn00100000

← Rn ← 0

MSB

SHAR

0100nnnn00100001

MSB

→ Rn → T

LSB

SHLL

0100nnnn00000000

← Rn ← 0

MSB

SHLR

0100nnnn00000001

→ Rn → T

LSB

SHLL2

0100nnnn00001000

Rn<<2

→ Rn

—

SHLR2

0100nnnn00001001

Rn>>2

→ Rn

—

SHLL8

0100nnnn00011000

Rn<<8

→ Rn

—

SHLR8

0100nnnn00011001

Rn>>8

→ Rn

—

SHLL16 Rn

0100nnnn00101000

Rn<<16

→ Rn

—

SHLR16 Rn

0100nnnn00101001

Rn>>16

→ Rn

—

Table 2.16

Branch Instructions

Instruction

Instruction Code

Operation

Executio

n Cycles T bit

label

10001011dddddddd

If T = 0, disp

×2 + PC → PC; if T = 1, nop 3/1*

—

label

10001001dddddddd

If T = 1, disp

×2 + PC → PC; if T = 0, nop 3/1*

—

BRA label

1010dddddddddddd

Delayed branch, disp

×2 + PC → PC

—

BSR label

1011dddddddddddd

Delayed branch, PC

→ PR, disp×2 + PC

→ PC

—

JMP @Rm

0100mmmm00101011

Delayed branch, Rm

→ PC

—

JSR @Rm

0100mmmm00001011

Delayed branch, PC

→ PR, Rm → PC

—

RTS

0000000000001011

Delayed branch, PR

→ PC

—

Note:

The execution state is three cycles when program branches, and one cycle when program

does not branch.

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