SH7021 datasheet(72/509 Pages) RENESAS

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3. Clears the vector base register (VBR) to H'00000000, and sets interrupt mask bits I3–I0 in the

status register (SR) to H'F (1111).

4. Loads the values read from the exception vector table into PC and SP and starts program

execution.

Further, make sure to carry out a power-on reset when turning on the power of the system.

4.2.3

Manual Reset

When the NMI pin is high, a low input at the

RES pin drives the chip into the manual reset state.

To be assured of resetting the LSI, drive the

RES pin low for at least 20 tcyc. A manual reset

initializes the internal state of the CPU and all registers of the on-chip peripheral modules except

the bus state controller, pin function controller and I/O ports. Since a manual reset does not affect

the bus state controller, the DRAM refresh control function operates even if the manual reset state

continues for a long time. When a manual reset is performed during the bus cycle, the manual

reset exception processing waits for the end of the bus cycle before beginning. The manual reset

thus cannot be used to abort the bus cycle. For the pin states during the manual reset state, see

appendix B, Pin States.

While the NMI pin remains low, if the

RES pin is held low for a certain time then driven high in

the manual reset state, manual reset exception processing begins. The CPU carries out the same

operations as for a power-on reset.

4.3

Address Errors

4.3.1

Address Error Sources

Address errors occur during instruction fetches and data reading/writing as shown in table 4.5.

SH7021 Datasheet(PDF) 72 Page - Renesas Technology Corp