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SH7021 Datasheet(PDF) 94 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 94 Page - Renesas Technology Corp |
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94 / 509 page  RENESAS 75 Section 6 User Break Controller (UBC) 6.1 Overview The user break controller (UBC) simplifies the debugging of user programs. Break conditions are set in the UBC and a user break interrupt request is sent to the CPU in response to the contents of a CPU or DMAC bus cycle. This function can implement an effective self-monitoring debugger, enabling a program to be debugged by itself without using a large in-circuit emulator. 6.1.1 Features • The following break conditions can be set: Address CPU cycle or DMA cycle Instruction fetch or data access Read or write Operand size (long word access, word access, or byte access) • When break conditions are met, a user break interrupt is generated. A user-created user break interrupt exception routine can then be executed. • When a break is set to a CPU instruction fetch, the break occurs just before the fetched instruction. 6.1.2 Block Diagram Figure 6.1 is the block diagram of the user break controller. |
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