SH7021 datasheet(14/509 Pages) RENESAS

14 / 509 page

8.2.2

Wait State Control Register 1 (WCR1)................................................................

8.2.3

Wait State Control Register 2 (WCR2)................................................................ 101

8.2.4

Wait State Control Register 3 (WCR3)................................................................ 103

8.2.5

DRAM Area Control Register (DCR).................................................................. 104

8.2.6

Refresh Control Register (RCR) .......................................................................... 107

8.2.7

Refresh Timer Control/Status Register (RTCSR) ................................................ 108

8.2.8

Refresh Timer Counter (RTCNT) ........................................................................ 110

8.2.9

Refresh Time Constant Register (RTCOR).......................................................... 112

8.2.10 Parity Control Register (PCR).............................................................................. 112

8.2.11 Notes on Register Access ..................................................................................... 114

8.3

Address Space Subdivision................................................................................................ 115

8.3.1

Address Spaces and Areas.................................................................................... 115

8.3.2

Bus Width ............................................................................................................. 117

8.3.3

Chip Select Signals (

CS0–CS7)............................................................................ 117

8.3.4

Shadows................................................................................................................ 118

8.3.5

Area Description .................................................................................................. 120

8.4

Accessing External Memory Space ................................................................................... 128

8.4.1

Basic Timing ........................................................................................................ 128

8.4.2

Wait State Control ................................................................................................ 129

8.4.3

Byte Access Control ............................................................................................. 133

8.5

DRAM Interface Operation ............................................................................................... 134

8.5.1

DRAM Adress Multiplexing ............................................................................... 134

8.5.2

Basic Timing ........................................................................................................ 136

8.5.3

Wait State Control ................................................................................................ 138

8.5.4

Byte Access Control ............................................................................................. 140

8.5.5

DRAM Burst Mode .............................................................................................. 142

8.5.6

Refresh Control .................................................................................................... 148

8.6

Address/Data Multiplexed I/O Space Access.................................................................... 151

8.6.1

Basic Timing ........................................................................................................ 152

8.6.2

Wait State Control ................................................................................................ 153

8.6.3

Byte Access Control ............................................................................................. 153

8.7

Parity Check and Generation ............................................................................................. 154

8.8

Warp Mode ........................................................................................................................ 154

8.9

Wait State Control ............................................................................................................. 155

8.10

Bus Arbitration .................................................................................................................. 157

8.10.1 The Operation of Bus Arbitration ........................................................................ 158

8.10.2

BACK Operation.................................................................................................. 159

8.11

Usage Notes ....................................................................................................................... 161

8.11.1 Usage Notes on Manual Reset.............................................................................. 161

8.11.2 Usage Notes on Parity Data Pins DPH and DPL ................................................. 164

8.11.3 Maximum Number of States from

BREQ Input to Bus Release ......................... 164

Section 9 Direct Memory Access Controller (DMAC) ......................................... 169

SH7021 Datasheet(PDF) 14 Page - Renesas Technology Corp

SH7021 Datasheet(HTML) 14 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL