SH7021 datasheet(96/509 Pages) RENESAS

96 / 509 page

RENESAS 77

Table 6.1

User Break Controller Registers

Name

Abbr.

R/W

Address*

Initial

Value

Bus width

Break address register high

BARH

R/W

H'5FFFF90

H'0000

8, 16, 32

Break address register low

BARL

R/W

H'5FFFF92

H'0000

8, 16, 32

Break address mask register high

BAMRH

R/W

H'5FFFF94

H'0000

8, 16, 32

Break address mask register low

BAMRL

R/W

H'5FFFF96

H'0000

8, 16, 32

Break bus cycle register

BBR

R/W

H'5FFFF98

H'0000

8, 16, 32

Note:

Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For details

on the register addresses, see section 8.3.5, Description of Areas.

6.2

6.2.1

Break Address Registers (BAR)

There are two break address registers—break address register H (BARH) and break address

stores the upper bits (bits 31–16) of the address of the break condition. BARL stores the lower bits

(bits 15–0) of the address of the break condition. A reset initializes both BARH and BARL to

H'0000. Neither is initialized in standby mode.

BARH: Break address register H.

Bit:

Bit name:

BA31

BA30

BA29

BA28

BA27

BA26

BA25

BA24

Initial value:

R/W:

R/W

Bit:

Bit name:

BA23

BA22

BA21

BA20

BA19

BA18

BA17

BA16

Initial value:

R/W:

R/W

•

BARH Bits 15–0 (break address 31–16 (BA31–BA16)): BA31–BA16 store the upper bit

values (bits 31–16) of the address of the break condition.

SH7021 Datasheet(PDF) 96 Page - Renesas Technology Corp

SH7021 Datasheet(HTML) 96 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL