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functions as a base address for the indirect GBR addressing mode to transfer data to the registers

of peripheral on-chip modules. The vector base register functions as the base address of the

exception processing vector area including interrupts.

9 8 765 4 3 2 1 0

MQ I3 I2 I1 I0

GBR

VBR

S bit: Used by the MAC instruction.

Reserved bits. These bits always read 0.

The write value should always be 0.

Bits I0–I3: Interrupt mask bits.

M and Q bits: Used by the DIV0U, DIV0S,

and DIV1 instructions.

Global base register (GBR):

Indicates the base address of the indirect

GBR addressing mode. The indirect GBR

addressing mode is used to transfer data

to the register areas peripheral on-chip

modules.

Vector base register (VBR):

Stores the base address of the exception

processing vector area.

SR: Status register

T bit: The MOVT, CMP, TAS, TST,

BT, BF, SETT, and CLRT instructions

use the T bit to indicate a true (1) or

false (0). The ADDV, ADDC, SUBV,

SUBC, DIV0U, DIV0S, DIV1, NEGC,

SHAR, SHAL, SHLR, SHLL, ROTR,

ROTL, ROTCR and ROTCL

instructions also use the T bit to indicate

carry/borrow or overflow/underflow

Figure 2.2 Control Registers

2.1.3

System Registers

System registers consist of four 32-bit registers: multiply and accumulate registers high and low

(MACH and MACL), procedure register (PR), and program counter (PC). The multiply and

accumulate registers store the results of multiply and accumulate operations. The procedure

program addresses to control the flow of the processing.

SH7021 Datasheet(PDF) 37 Page - Renesas Technology Corp