SH7021 datasheet(15/509 Pages) RENESAS

15 / 509 page

9.1

Overview............................................................................................................................ 169

9.1.1

Features ................................................................................................................ 169

9.1.2

Block Diagram...................................................................................................... 170

9.1.3

Pin Configuration ................................................................................................. 172

9.1.4

9.2

Register Descriptions......................................................................................................... 174

9.2.1

DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 174

9.2.2

DMA Destination Address Registers 0-3 (DAR0–DAR3) .................................. 174

9.2.3

DMA Transfer Count Registers 0–3 (TCR0–TCR3) ........................................... 175

9.2.4

DMA Channel Control Registers 0–3 (CHCR0–CHCR3) ................................... 175

9.2.5

DMA Operation Register (DMAOR) ................................................................... 180

9.3

Operation ........................................................................................................................... 182

9.3.1

DMA Transfer Flow ............................................................................................. 182

9.3.2

DMA Transfer Requests....................................................................................... 184

9.3.3

Channel Priority.................................................................................................... 186

9.3.4

DMA Transfer Types ........................................................................................... 191

9.3.5

Number of Bus Cycle States and

DREQ Pin Sample Timing.............................. 198

9.3.6

DMA Transfer Ending Conditions ....................................................................... 205

9.4

Examples of Use................................................................................................................ 206

9.4.1

DMA Transfer between On-Chip RAM and a Memory-Mapped

External Device .................................................................................................... 206

9.4.2

Example of DMA Transfer between On-Chip SCI and External Memory.......... 207

9.5

Cautions ............................................................................................................................. 208

Section 10 16-Bit Integrated-Timer Pulse Unit (ITU) ............................................ 213

10.1

Overview............................................................................................................................ 213

10.1.1 Features ................................................................................................................ 213

10.1.2 Block Diagram...................................................................................................... 216

10.1.3 Input/Output Pins.................................................................................................. 221

10.1.4 Register Configuration ......................................................................................... 222

10.2

ITU Register Descriptions ................................................................................................. 224

10.2.1 Timer Start Register (TSTR)................................................................................ 224

10.2.2 Timer Synchro Register (TSNC).......................................................................... 226

10.2.3 Timer Mode Register (TMDR) ............................................................................ 227

10.2.4 Timer Function Control Register (TFCR)............................................................ 230

10.2.5 Timer Output Control Register (TOCR) .............................................................. 231

10.2.6 Timer Counters (TCNT)....................................................................................... 232

10.2.7 General Registers A and B (GRA and GRB) ....................................................... 233

10.2.8 Buffer Registers A and B (BRA, BRB)................................................................ 234

10.2.9 Timer Control Register (TCR) ............................................................................. 235

10.2.10 Timer I/O Control Register (TIOR) ..................................................................... 237

10.2.11 Timer Status Register (TSR) ................................................................................ 239

10.2.12 Timer Interrupt Enable Register (TIER) .............................................................. 240

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