SH7021 datasheet(62/509 Pages) RENESAS

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Table 2.18

Operation Code Map (cont)

Instruction Code

Fx: 0000

Fx: 0001

Fx: 0010

Fx: 0011–1111

MSB

LSB MD: 00

MD: 01

MD: 10

MD: 11

1100 00MD

imm/disp

MOV.B R0,@

(disp:8,GBR)

MOV.W R0,@

(disp:8,GBR)

MOV.L R0,@

(disp:8,GBR)

TRAPA #imm:8

1100 01MD

disp

MOV.B

@(disp:8,

GBR),R0

MOV.W

@(disp:8,

GBR),R0

MOV.L

@(disp:8,

GBR),R0

MOVA

@(disp:8,

PC),R0

1100 10MD

imm

TST

#imm:8,R0

AND

#imm:8,R0

XOR

#imm:8,R0

1100 11MD

imm

TST.B

#imm:8,

@(R0,GBR)

AND.B

#imm:8,

@(R0,GBR)

XOR.B

#imm:8,

@(R0,GBR)

OR.B

#imm:8,

@(R0,GBR)

1101 Rn

disp

MOV.L @(disp:8,PC),Rn

1110 Rn

imm

MOV

#imm:8,Rn

1111

...

2.5

CPU State

2.5.1

State Transitions

The CPU has five processing states: reset, exception processing, bus release, program execution

and power-down. The transitions between the states are shown in figure 2.6. For more information

on the reset and exception processing states, see section 4, Exception Processing. For details on

the power-down states, see section 19, Power Down States.

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