SH7021 datasheet(99/509 Pages) RENESAS

99 / 509 page

80 RENESAS

Bit:

Bit name:

—

Initial value:

R/W:

—

Bit:

Bit name:

CD1

CD0

ID1

ID0

RW1

RW0

SZ1

SZ0

Initial value:

R/W:

R/W

•

Bits 15–8 (reserved): These bits always read as 0. The write value should always be 0.

•

Bits 7 and 6 (CPU cycle/DMA cycle select (CD1 and CD0)): CD1 and CD0 select whether to

break on CPU and/or DMA bus cycles.

Bit 7: CD1

Bit 6: CD0

Description

No break interrupt occurs (initial value)

Break only on CPU cycles

Break only on DMA cycles

Break on both CPU and DMA cycles

•

Bits 5 and 4 (instruction fetch/data access select (ID1, ID0)): ID1, ID0 select whether to break

on instruction fetch and/or data access bus cycles.

Bit 5: ID1

Bit 4: ID0

Description

No break interrupt occurs (initial value)

Break only on instruction fetch cycles

Break only on data access cycles

Break on both instruction fetch and data access cycles

SH7021 Datasheet(PDF) 99 Page - Renesas Technology Corp

SH7021 Datasheet(HTML) 99 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL