 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SH7021 Datasheet(PDF) 101 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
SH7021 Datasheet(HTML) 101 Page - Renesas Technology Corp |
|
|
101 / 509 page  82 RENESAS 3. When receiving the user break interrupt request, the interrupt controller checks its priority level. The user break interrupt has priority level 15, so it is accepted only if the interrupt mask level in bits I3–I0 in the status register (SR) is 14 or lower. When the I3–I0 bit level is 15, the user break interrupt cannot be accepted but it is held pending until user break interrupt exception processing is carried out. NMI exception processing sets I3–I0 to level 15, so a user break cannot occur during the NMI service routine unless the NMI service routine itself begins by reducing I3–I0 to level 14 or lower. Section 5, Interrupt Controller, described the handling of priority levels in greater detail. 4. The INTC sends a request signal for a user break interrupt to the CPU. When the CPU receives it, it starts user break interrupt exception processing. Section 5.4, Interrupt Operation, describes interrupt exception processing in more detail. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
