SH7021 datasheet(93/509 Pages) RENESAS

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FD E

MM E

Interrupt accepted

IRQ

m1 m2 1 m3 1

5 + m1 + m2 + m3

Instruction (instruction replaced by

interrupt exception handling)

Overrun fetch

(edge)

(level)

Interrupt service routine—

first instruction

When m1 = m2 = m3, the interrupt response time is 11 cycles.

F (Instruction fetch)

Instruction fetched from memory where program is stored.

D (Instruction decoding)

The fetched instruction is decoded.

E (Instruction execution)

Data operations and address calculations are performed

according to the decoded results.

M (Memory access)

Data in memory is accessed.

Note: For the interrupt acceptance timing, see table 4.1, Exception Source Detection and

Exception Handling Start Timing, in section 4.1.2, Exception Handling Operation.

IRQOUT

Figure 5.4 Example of Pipelining in IRQ Interrupt Acceptance

5.6

Usage Notes

When the following operations are performed in the order shown when a pin to which IRQ input is

assigned is designated as a general input pin by the pin function controller (PFC) and inputs a low-

level signal, the IRQ falling edge is detected, and an interrupt request is detected, immediately

after the setting in (b) is performed:

•

An interrupt control register (ICR) setting is made so that an interrupt is detected at the falling

edge of IRQ.

…… (a)

•

The function of pins to which IRQ input is assigned is switched from general input to IRQ

input by a pin function controller (PFC) setting.

…… (b)

Therefore, when switching the pin function from general input pin to IRQ input, the pin function

controller (PFC) setting should be changed to IRQ input while the pin to which IRQ input is

assigned is high.

SH7021 Datasheet(PDF) 93 Page - Renesas Technology Corp

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