SH7021 datasheet(63/509 Pages) RENESAS

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42 RENESAS

RES

= 0, NMI = 1

RES

= 0, NMI = 0

Power-on reset state

Manual reset state

Sleep mode

Standby mode

Program execution state

Bus release state

Exception processing state

RES

= 1,

NMI = 0

RES

= 1,

NMI = 1

When an interrupt source

or DMA address error occurs

NMI interrupt

source occurs

Exception

processing

ends

Bus request

generated

Exception

processing

source occurs

Bus request

cleared

Bus request

generated

Bus request

cleared

SBY bit cleared for

SLEEP instruction

SBY bit set

for SLEEP

instruction

From any state when

RES

= 0 and NMI = 1

From any state when

RES

= 0 and NMI = 0

Reset states

Power-down state

Bus request

generated

Bus request

cleared

Figure 2.6 Transitions Between Processing States

Reset State: In the reset state the CPU is reset. This occurs when the

RES pin level goes low.

When the NMI pin is high, the result is a power-on reset; when it is low, a manual reset will

occur.When turning on the power, make sure to carry out a power-on reset.

SH7021 Datasheet(PDF) 63 Page - Renesas Technology Corp

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