SH7021 datasheet(378/509 Pages) RENESAS

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Table 13.7

Maximum Bit Rates during External Clock Input (Clocked Synchronous Mode)

φ (MHz)

External Input Clock (MHz)

Maximum Bit Rate (bits/s)

0.3333

333333.3

0.6667

666666.7

1.0000

1000000.0

1.3333

1333333.3

1.6667

1666666.7

2.0000

2000000.0

2.3333

2333333.3

2.6667

2666666.7

3.0000

3000000.0

3.3333

3333333.3

13.3

Operation

13.3.1

Overview

The SCI has an asynchronous mode in which characters are synchronized individually, and a

clocked synchronous mode in which communication is synchronized with clock pulses. Serial

communication is possible in either mode. Asynchronous/clocked synchronous mode and the

communication format are selected in the serial mode register (SMR), as shown in table 13.8. The

SCI clock source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and

CKE0 bits in the serial control register (SCR), as shown in table 13.9.

Asynchronous Mode:

•

Data length is selectable: seven or eight bits.

•

Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The

preceding selections constitute the communication format and character length.

•

In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors

(ORER), and the break state.

•

An internal or external clock can be selected as the SCI clock source.

 When an internal clock is selected, the SCI operates using the on-chip baud rate generator,

and can output a serial clock signal with a frequency matching the bit rate.

 When an external clock is selected, the external clock input must have a frequency 16 times

the bit rate. (The on-chip baud rate generator is not used.)

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