PCI2040 datasheet(39/79 Pages) TI

39 / 79 page

4–7

4.11 HPI CSR Memory Base Address Register

The HPI CSR memory base address register provides a method of allowing the host to map the PCI2040’s HPI CSR

registers into host memory space.

Bit

Name

HPI CSR memory base address

Type

Default

Bit

Name

HPI CSR memory base address

Type

Default

HPI CSR memory base address

Type:

Read-only, Read/Write

Offset:

10h

Default:

0000 0000h

Table 4–5. HPI CSR Memory Base Address Register

BIT

FIELD NAME

TYPE

DESCRIPTION

31–12

AVAIL_ADD

Available address bits. These bits can be written by the host in order to allow initialization of the base

address at startup. The PCI memory address space is on the 4-Kbyte boundary.

11–4

UNAVAIL_ADD

Unavailable address bit. Bits 11–4 return 00h when read.

PREFETCHABLE

Prefetchable. This bit is hardwired to 0 in the PCI2040.

2–1

TYPE

Type. Bits 2 and 1 indicate the size of the base address and how it can be mapped into the host memory.

These bits are hardwired to 00 in the PCI2040 to indicate that a 32-bit base address register is used

which can be located anywhere in memory.

MEM_IND

Memory space indicator. This bit indicates whether the base address maps into the host’s memory or

I/O space. This bit is hardwired to 0 in the PCI2040 to indicate that this base address is valid only for

memory accesses.

PCI2040 Datasheet(PDF) 39 Page - Texas Instruments

PCI2040 Datasheet(HTML) 39 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL