PCI2040 datasheet(63/79 Pages) TI

63 / 79 page

6–5

6.2.6

HPI Memory Access During Reset

The DSP is not operational during reset, but the host can access the HPI hereby allowing the program or data to be

downloaded to the HPI memory. However to use this capability, it is convenient for the host to control the DSP’s reset.

Initially, the host stops accessing the HPI at least six DSP periods before driving the DSP reset line low. The HPI mode

is set to HOM during the reset and the host can start accessing the HPI after four DSP periods.

Once the host has finished downloading into the HPI memory, the host stops accessing the HPI and drives the C5x

reset line. At least 20 clock periods after the reset line rising high, the host can again start accessing the HPI. HPI

mode is automatically set to SAM upon exiting reset.

6.2.7

Examples of Transactions Targeting the C54X

In order to describe how the PCI2040 translates PCI cycles into 8-bit host port transactions the following examples

are provided. In each example, the following information is common:

The control space base address (PCI offset 14h) contains FFEF0000h.

There are four TMS320C5410s behind the PCI2040.

6.2.7.1 PCI Word Write

In the first example depicted in Figure 6–2, a PCI write transaction with address FFEF1800, byte enables of 1100b,

and a single data phase of the PCI bus occurs. The data is DDCCBBAAh. The PCI2040 takes this PCI transaction

and translates it to an 8-bit host port transaction. The event flow is as follows:

The host port is idle.

HCNTL0 and HCNTL1 are driven high indicating to the C5410 that this transaction is going to target the

HPID without auto-increment enabled. The HR/W is driven low indicating to the C5410 that this transaction

is a write.

HCS0 is asserted indicating that this transaction is targeting DSP0. The first byte or half-word is driven onto

the HAD bus. Notice the upper eight data lines (HAD15–HAD8) are not used. Only the lower eight data lines

are used when communicating with the C5410. Also, during clock 3, the HDS is asserted. During this time,

the C5410 latches the values of HCNTL1, HCNTL0, HWIL, and HR/W.

The PCI2040 samples the state of HRDY5X0. If the C5410 indicates it is not ready, then the PCI2040 waits

until the C5410 indicates it is ready before it deasserts HDS and HWIL.

Because the state of the HRDY5X0 signal indicates the C5410 is ready, the PCI2040 deasserts HDS. The

C5410 latches the data, AAh, on the rising edge of HDS. The HWIL is driven high.

During clock 6, the PCI2040 starts driving the second byte or half word onto the HAD bus. Please note that

the PCI bus uses little endian notation. For this reason, the PCI2040 transfers the least significant byte first

followed by the next least significant byte.

Same as Step 4.

Same as Step 5 except the data latched is BBh and the HCS0 is deasserted indicating the end of the

transaction.

PCI2040 Datasheet(PDF) 63 Page - Texas Instruments